Full Turnkey Service

Advanced package & silicon co-design process achieves optimum solution at a lower cost

Wafer Bump
Experienced in a? wide range of wafer bump alloys and processes – Electroplated process for SnPb, Pb-free, and Cu pillar bumps
Full service wafer bumping with Polyimide/PBO dielectric options for wafer repassivation and redistribution layer (RDL)
Fine pitch bumps down to 0.35mm (array and peripheral)
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Copyright @ Jiangsu Changjiang Electronics Technology Co., Ltd 蘇ICP備05082751號32028102000607

Copyright @ Jiangsu Changjiang Electronics Technology Co., Ltd
蘇ICP備05082751號 32028102000607

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